Ito Hideo | Graduate School Of Advanced Integration Sci. Chiba Univ.

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概要

• ITO Hideoの詳細を見る
• 同名の論文著者
• Graduate School Of Advanced Integration Sci. Chiba Univ.の論文著者

関連著者

• Ito Hideo

  Graduate School Of Advanced Integration Sci. Chiba Univ.

• Namba Kazuteru

  Graduate School Of Advanced Integration Sci. Chiba Univ.

• ITO Hideo

  Graduate School of Advanced Integration Science, Chiba University

• Namba Kazuteru

  Graduate School Of Advanced Integration Science Chiba University

• Ito Hideo

  Graduate School Of Advanced Integration Science Chiba University

• NAMBA Kazuteru

  Graduate School of Advanced Integration Science, Chiba University

• Namba Kazuteru

  Chiba Univ. Chiba‐shi Jpn

• Ito Hideo

  Chiba Univ. Chiba‐shi Jpn

• SBIAI Takieddine

  Graduate School of Advanced Integration Science, Chiba University

• KATOH Kentaroh

  Graduate School of Science and Technology, Chiba University

• Katoh Kentaroh

  Graduate School Of Science And Technology Chiba University

• Zeng Gang

  Graduate School Of Information Science Nagoya University

• Kitakami Masato

  Graduate School Of Advanced Integration Science Chiba University

• Kitakami Masato

  Chiba Univ. Chiba‐shi Jpn

• CAI Bochuan

  Graduate School of Science and Technology, Chiba University

• Cai Bochuan

  Graduate School Of Science And Technology Chiba University

• NAKASHIMA Kengo

  Graduate School of Advanced Integration Science, Chiba University

• Nakashima Kengo

  Graduate School Of Advanced Integration Science Chiba University

• Ito Hideo

  Faculty Of Engineering Chiba University

• Ruan Shuangyu

  Graduate School Of Advanced Integration Science Chiba University

• ZENG Gang

  Faculty of Engineering, Chiba University

• TAKASHINA Nobuhide

  Graduate School of Advanced Integration Science, Chiba University

• ZHANG Wenpo

  Graduate School of Advanced Integration Science, Chiba University

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著作論文

• BILBO FF with soft error correcting capability (コンピュータシステム)
• BILBO FF with soft error correcting capability (ディペンダブルコンピューティング)
• Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Single-Event-Upset Tolerant RS Flip-Flop with Small Area
• A Checkpointing Method with Small Checkpoint Latency
• Low-Cost IP Core Test Using Tri-Template-Based Codes
• Construction of BILBO FF with Soft-Error-Tolerant Capability
• Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism
• Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
• Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

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