A Checkpointing Method with Small Checkpoint Latency

スポンサーリンク

概要

• 論文の詳細を見る

• The cost of checkpointing consists of checkpoint over-head and checkpoint latency. The former is the time to stop the process for checkpointing. The latter is the time to complete the checkpointing including background checkpointing which stores memory pages. The large checkpoint latency increases the possibility that the error occurs in back-ground checkpointing, which leads to long rollback distance. The method for small checkpoint latency has not been proposed yet. This paper proposes a checkpointing method which achieves small checkpoint latency. The proposed method divides a checkpoint interval into several subcheckpoint intervals. By using the history of memory page modification in subcheckpoint intervals, the proposed method saves some pages which are not expected to be modified in the rest of checkpoint interval in advance. Computer simulation says that the proposed method can reduce the checkpoint latency by 25% comparing to the existing methods.

• （社）電子情報通信学会の論文
• 2008-03-01

著者

• ITO Hideo

  Graduate School of Advanced Integration Science, Chiba University

• Kitakami Masato

  Graduate School Of Advanced Integration Science Chiba University

• Kitakami Masato

  Chiba Univ. Chiba‐shi Jpn

• CAI Bochuan

  Graduate School of Science and Technology, Chiba University

• Cai Bochuan

  Graduate School Of Science And Technology Chiba University

• Ito Hideo

  Graduate School Of Advanced Integration Science Chiba University

• Ito Hideo

  Graduate School Of Advanced Integration Sci. Chiba Univ.

関連論文

• Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Grid Monitoring System based on GMA
• BILBO FF with soft error correcting capability (コンピュータシステム)
• BILBO FF with soft error correcting capability (ディペンダブルコンピューティング)
• Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
• A Class of Error Locating Codes : SEC - S_EL Codes
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Single-Event-Upset Tolerant RS Flip-Flop with Small Area
• Trust Management of Grid System Embedded with Resource Management System
• Dependability Improvement for PPM Compressed Data by Using Compression Pattern Matching
• Burst Error Recovery Method for LZSS Coding
• A Checkpointing Method with Small Checkpoint Latency
• Burst Error Recovery for Huffman Coding(Algorithm Theory)
• Low-Cost IP Core Test Using Tri-Template-Based Codes
• Construction of BILBO FF with Soft-Error-Tolerant Capability
• Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
• Integrating trust into scheduling algorithms in Grid system (ディペンダブルコンピューティング)
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism
• Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
• Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
• Mobile device prediction for location-based cloud service

もっと見る 閉じる

スポンサーリンク