Namba Kazuteru | Graduate School Of Advanced Integration Sci. Chiba Univ.

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• 同名の論文著者
• Graduate School Of Advanced Integration Sci. Chiba Univ.の論文著者

関連著者

• Namba Kazuteru

  Graduate School Of Advanced Integration Sci. Chiba Univ.

• Ito Hideo

  Graduate School Of Advanced Integration Sci. Chiba Univ.

• Namba Kazuteru

  Graduate School Of Advanced Integration Science Chiba University

• ITO Hideo

  Graduate School of Advanced Integration Science, Chiba University

• NAMBA Kazuteru

  Graduate School of Advanced Integration Science, Chiba University

• Ito Hideo

  Graduate School Of Advanced Integration Science Chiba University

• Namba Kazuteru

  Chiba Univ. Chiba‐shi Jpn

• Ito Hideo

  Chiba Univ. Chiba‐shi Jpn

• SBIAI Takieddine

  Graduate School of Advanced Integration Science, Chiba University

• KATOH Kentaroh

  Graduate School of Science and Technology, Chiba University

• Fujiwara Eiji

  Graduate School Of Information Science And Engineering Tokyo Institute Of Technology

• Katoh Kentaroh

  Graduate School Of Science And Technology Chiba University

• Kitakami Masato

  Vlsi Design And Education Center The University Of Tokyo

• Namba Kazuteru

  Graduate School Of Information Science And Engineering Tokyo Institute Of Technology

• NAKASHIMA Kengo

  Graduate School of Advanced Integration Science, Chiba University

• Nakashima Kengo

  Graduate School Of Advanced Integration Science Chiba University

• Ruan Shuangyu

  Graduate School Of Advanced Integration Science Chiba University

• NAMBA Kazuteru

  Graduate School of Information Science and Engineering, Tokyo Institute of Technology

• TAKASHINA Nobuhide

  Graduate School of Advanced Integration Science, Chiba University

• ZHANG Wenpo

  Graduate School of Advanced Integration Science, Chiba University

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著作論文

• BILBO FF with soft error correcting capability (コンピュータシステム)
• BILBO FF with soft error correcting capability (ディペンダブルコンピューティング)
• Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Single-Event-Upset Tolerant RS Flip-Flop with Small Area
• Parallel Decoding for Burst Error Control Codes
• Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities
• Construction of BILBO FF with Soft-Error-Tolerant Capability
• Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism
• Unequal Error Control Codes with Two-Level Burst and Bit Error Correcting Capabilities
• Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
• Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

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