Parallel Decoding for Burst Error Control Codes

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概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 2002-11-01

著者

• Fujiwara Eiji

  Graduate School Of Information Science And Engineering Tokyo Institute Of Technology

• Kitakami Masato

  Vlsi Design And Education Center The University Of Tokyo

• Namba Kazuteru

  Graduate School Of Advanced Integration Science Chiba University

• Namba Kazuteru

  Graduate School Of Advanced Integration Sci. Chiba Univ.

• NAMBA Kazuteru

  Graduate School of Information Science and Engineering, Tokyo Institute of Technology

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• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Design for Delay Fault Testability of 2-Rail Logic Circuits
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• Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities
• Unequal Error Protection in Ziv-Lempel Coding(Dependable Communication)(Dependable Computing)
• Escape and Restoration Routing : Suspensive Deadlock Recovery in Interconnection Networks
• Construction of BILBO FF with Soft-Error-Tolerant Capability
• Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• A Dynamically Configurable NoC Test Access Mechanism
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• Unequal Error Control Codes with Two-Level Burst and Bit Error Correcting Capabilities
• Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA
• Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

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