Escape and Restoration Routing : Suspensive Deadlock Recovery in Interconnection Networks
スポンサーリンク
概要
- 論文の詳細を見る
In interconnection networks, deadlock recovery has been studied in routine strategy. The routine strategy for the deadlock recovery is intended to optimize the routine performance when deadlocks do not occur. On the other hand, it is important to improve the rooting performance by handling deadlocks if they occur. In this paper, a rooting strategy for suspensive deadlock recovery called an escape-restoration rooting is proposed and its performance is evaluated. In the principle of the proposed techniques, a small amount of exclusive buffer (escapebuffer) at each router is prepared for handling one of deadlocked packets. The transmission of the packet is suspended by temporarily escaping it to the escape-buffer. After the other deadlocked packets were sent, the suspended transmission resumes by restoring the escaped packet. Evaluation results show that the proposed techniques can improve the routing performance more than that of the previous recovery-based techniques in handling deadlocks.
- 社団法人電子情報通信学会の論文
- 2002-05-01
著者
-
Kitakami Masato
Vlsi Design And Education Center The University Of Tokyo
-
Kitakami Masato
Vlsi Design And Eduration Center The University Of Tokyo
-
ITO Hideo
Faculty of Engineering, Chiba University
-
Takabatake Toshinori
Graduate School Of Science And Technology Chiha University
-
Ito Hideo
Faculty Of Engineering Chiba University
-
Ito Hideo
Faculty Of Engineering Chiha University
関連論文
- X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability(Dependable Computing)
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks (Special Issue on Fault-Tolerant Computing)
- Output Smoothing: A learning Algorithm for Fault Tolerant Neural Networks
- Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core(Dependable Computing)
- Scan Design for Two-Pattern Test without Extra Latches(Dependable Computing)
- Parallel Decoding for Burst Error Control Codes
- Fault-Tolerant Routing Algorithms for Hypercube Interconnection Networks
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- Escape and Restoration Routing : Suspensive Deadlock Recovery in Interconnection Networks
- Low-Cost IP Core Test Using Tri-Template-Based Codes
- On the Activation Function and Fault Tolerance in Feedforward Neural Networks
- Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
- Proposal of Testable Multi-Context FPGA Architecture(Dependable Computing)
- Redundant Design for Wallace Multiplier(Dependable Computing)