FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
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概要
- 論文の詳細を見る
This paper presents a new approach for test and diagnosis of faults in field programmable gate arrays (FPGAs). The new method exploits the configurability and the programmability of SRAM-based FPGAs and implements connections between the configurable logic blocks (CLBs) as a binary tree. The proposed scheme is based on BIST (built-in-self-testing) method, and the implementation does not need any hardware overhead. It is proved that this approach detects the multiple faults and locates single faults. The method is also able to give the exact locations of one part of multiple faults, while it gives some possible locations for other multiple faults. The simulation results indicate that the proposed method covers 100% of the modelled faults.
- 社団法人電子情報通信学会の論文
- 1999-02-04
著者
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Ito Hideo
The Authors Are With The Faculty Of Engineering Chiba University
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ITO Hideo
Faculty of Engineering, Chiba University
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Ohmameuda Toshiaki
The Authors Are With The Faculty Of Engineering Chiba University
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Ohmameuda Toshiaki
Faculty Of Engineering Chiba University
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Doumar Abderrahim
Graduate School of Science and Technology, Chiba University, Japan
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Doumar Abderrahim
Graduate School Of Science And Technology Chiba University
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Ito Hideo
Faculty Of Engineering Chiba University
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