Fast Testable Design for SRAM-Based FPGAs

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概要

• 論文の詳細を見る

• This paper presents a new design for testing SRAM-based field programmable gate arrays(FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks(CLBs)or the chip size increases.

• 社団法人電子情報通信学会の論文
• 2000-05-25

著者

• Ito Hideo

  The Authors Are With The Faculty Of Engineering Chiba University

• Ohmameuda Toshiaki

  The Authors Are With The Faculty Of Engineering Chiba University

• DOUMAR Abderrahim

  The author is with the Graduate School of Science and Technology, Chiba University

• Doumar Abderrahim

  The Author Is With The Graduate School Of Science And Technology Chiba University

• Ito Hideo

  The Author Is With The Faculty Of Engineering Chiba University

関連論文

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• Design of an Automatic Testing for FPGAs (特集 VLSIプロセッサ及び新アーキテクスチャLSI技術、一般)
• Design of an Automatic Testing for FPGAs (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)
• D-10-3 An Autotest Design for FPGAs
• FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
• Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data

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