HCC : Generalized Hierarchical Completely-Connected Networks

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, a new network structure called generalized Hierarchical Completely-Connected networks(HCCs) is proposed, and its properties and features are evaluated. Simple routing strategies for HCCs are also developed for shortest-paths routing algorithms. A set of HCCs constructed by the proposed method includes some conventional hierarchical networks, then it is called generalized one. The construction of an HCC starts from a basic block(a level-1 block)which consists of n nodes of constant degree. Then a level-h block for h≥2 is constructed recursively by interconnecting any pair of macro nodes(n level-(h-1)blocks)completely. An HCC has a constant node-degree regardless of an increase in its size(the number of nodes). Furthermore, since an HCC has a hierarchically structured topology and the feature of uniformity, a wide variety of inter-cluster connections is possible. Evaluation results show that an HCC is suitable for very large computer systems.

• 社団法人電子情報通信学会の論文
• 2000-06-25

著者

• Ito Hideo

  The Authors Are With The Faculty Of Engineering Chiba University

• Kaneko Keiichi

  The Author Is With The Faculty Of Technology Tokyo University Of Agri.and Tech.

• TAKABATAKE Toshinori

  The author is with the Graduate School of Science and Technology, Chiba University

• Takabatake T

  Chiba Univ. Chiba‐shi Jpn

• Ito Hideo

  The Author Is With The Faculty Of Engineering Chiba University

• ITO Hideo

  The author is with the Faculty of Engineering, Chiba University

関連論文

• HCC : Generalized Hierarchical Completely-Connected Networks
• Fast Testable Design for SRAM-Based FPGAs
• Design of an Automatic Testing for FPGAs (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)
• Design of an Automatic Testing for FPGAs (特集 VLSIプロセッサ及び新アーキテクスチャLSI技術、一般)
• Design of an Automatic Testing for FPGAs (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)
• D-10-3 An Autotest Design for FPGAs
• FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
• Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data

スポンサーリンク