Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data

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概要

• 論文の詳細を見る

• The homogeneous structure of field programmable gate arrays(FPGAs)suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks(CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources(king-shifting and Horse-allocation)are introduced and compared.

• 社団法人電子情報通信学会の論文
• 2000-05-25

著者

• Doumar Abderrahim

  The Author Is With The Graduate School Of Science And Technology Chiba University

• Ito Hideo

  The Author Is With The Faculty Of Engineering Chiba University

関連論文

• HCC : Generalized Hierarchical Completely-Connected Networks
• Fast Testable Design for SRAM-Based FPGAs
• Defect and Fault Tolerance SRAM-Based FPGAs by Shifting the Configuration Data

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