FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
スポンサーリンク
概要
- 論文の詳細を見る
This paper presents a new approach for test and diagnosis of faults in field programmable gate arrays (FPGAs). The new method exploits the configurability and the programmability of SRAM-based FPGAs and implements connections between the configurable logic blocks (CLBs) as a binary tree. The proposed scheme is based on BIST (built-in-self-testing) method, and the implementation does not need any hardware overhead. It is proved that this approach detects the multiple faults and locates single faults. The method is also able to give the exact locations of one part of multiple faults, while it gives some possible locations for other multiple faults. The simulation results indicate that the proposed method covers 100% of the modelled faults.
- 一般社団法人情報処理学会の論文
- 1999-02-04
著者
-
ITO Hideo
Faculty of Engineering, Chiba University
-
Ohmameuda Toshiaki
Faculty Of Engineering Chiba University
-
Doumart Abderrahim
Graduate School of Science and Technology, Chiba University
-
Doumart Abderrahim
Graduate School Of Science And Technology Chiba University
-
Ito Hideo
Faculty Of Engineering Chiba University
関連論文
- X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability(Dependable Computing)
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks (Special Issue on Fault-Tolerant Computing)
- Output Smoothing: A learning Algorithm for Fault Tolerant Neural Networks
- Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core(Dependable Computing)
- Scan Design for Two-Pattern Test without Extra Latches(Dependable Computing)
- Fault-Tolerant Routing Algorithms for Hypercube Interconnection Networks
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- Escape and Restoration Routing : Suspensive Deadlock Recovery in Interconnection Networks
- Low-Cost IP Core Test Using Tri-Template-Based Codes
- On the Activation Function and Fault Tolerance in Feedforward Neural Networks
- Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
- Proposal of Testable Multi-Context FPGA Architecture(Dependable Computing)
- Redundant Design for Wallace Multiplier(Dependable Computing)