Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
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概要
- 論文の詳細を見る
In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.
- 一般社団法人電子情報通信学会の論文
- 2005-09-01
著者
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Namba Kazuteru
Chiba Univ. Chiba‐shi Jpn
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Namba Kazuteru
Faculty Of Engineering Chiba University
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Ito Hideo
Faculty Of Engineering Chiba University
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