Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
スポンサーリンク
概要
- 論文の詳細を見る
This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
著者
-
Namba Kazuteru
Chiba Univ. Chiba‐shi Jpn
-
NAMBA Kazuteru
Graduate School of Advanced Integration Science, Chiba University
-
ITO Hideo
Graduate School of Advanced Integration Science, Chiba University
関連論文
- Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
- Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
- Design for Delay Fault Testability of 2-Rail Logic Circuits
- Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
- BILBO FF with soft error correcting capability (コンピュータシステム)
- BILBO FF with soft error correcting capability (ディペンダブルコンピューティング)
- Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
- Design for Delay Fault Testability of 2-Rail Logic Circuits
- Single-Event-Upset Tolerant RS Flip-Flop with Small Area
- A Checkpointing Method with Small Checkpoint Latency
- Construction of BILBO FF with Soft-Error-Tolerant Capability
- Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
- A Dynamically Configurable NoC Test Access Mechanism
- A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
- Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
- Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability