Design for Delay Fault Testability of 2-Rail Logic Circuits

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概要

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• This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

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著者

• Namba Kazuteru

  Chiba Univ. Chiba‐shi Jpn

• NAMBA Kazuteru

  Graduate School of Advanced Integration Science, Chiba University

• ITO Hideo

  Graduate School of Advanced Integration Science, Chiba University

• KATOH Kentaroh

  Graduate School of Science and Technology, Chiba University

関連論文

• Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
• Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• BILBO FF with soft error correcting capability (コンピュータシステム)
• BILBO FF with soft error correcting capability (ディペンダブルコンピューティング)
• Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
• Design for Delay Fault Testability of 2-Rail Logic Circuits
• Single-Event-Upset Tolerant RS Flip-Flop with Small Area
• A Checkpointing Method with Small Checkpoint Latency
• Construction of BILBO FF with Soft-Error-Tolerant Capability
• Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
• A Dynamically Configurable NoC Test Access Mechanism
• A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
• Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF
• Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

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