Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
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概要
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The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.
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著者
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Namba Kazuteru
Chiba Univ. Chiba‐shi Jpn
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NAMBA Kazuteru
Graduate School of Advanced Integration Science, Chiba University
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ITO Hideo
Graduate School of Advanced Integration Science, Chiba University
関連論文
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- Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
- Design for Delay Fault Testability of 2-Rail Logic Circuits
- Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
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- Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
- Design for Delay Fault Testability of 2-Rail Logic Circuits
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- A Dynamically Configurable NoC Test Access Mechanism (VLSI設計技術)
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