Proposal of Testable Multi-Context FPGA Architecture(Dependable Computing)
スポンサーリンク
概要
- 論文の詳細を見る
Multi-context FPGAs allow very quick reconfiguration by storing multiple configuration data at the same time. While testing for FPGAs with single-context memories has already been studied by many researchers, testing for multi-context FPGAs has not been proposed yet. This paper presents an architecture of testable multi-context FPGAs. In the proposed multi-context FPGA, configuration data stored in a context can be copied into another context. This paper also shows testing of the proposed multi-context FPGA. The proposed testing uses the testing for the traditional FPGAs with single-context. The testing is capable of detecting single stuck-at faults and single open faults which affect normal operations. The number of test configurations for the proposed testing is at most two more than that for the testing of FPGAs with single-context memories. The area overhead of the proposed architecture is 7% and 4% of the area of a multi-context FPGA without the proposed architecture when the number of contexts in a configuration memory is 8 and 16, respectively.
- 一般社団法人電子情報通信学会の論文
- 2006-05-01
著者
-
Namba Kazuteru
Faculty Of Engineering Chiba University
-
Ito Hideo
Faculty Of Engineering Chiba University
関連論文
- X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability(Dependable Computing)
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks
- A Learning Algorithm for Fault Tolerant Feedforward Neural Networks (Special Issue on Fault-Tolerant Computing)
- Output Smoothing: A learning Algorithm for Fault Tolerant Neural Networks
- Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core(Dependable Computing)
- Scan Design for Two-Pattern Test without Extra Latches(Dependable Computing)
- Fault-Tolerant Routing Algorithms for Hypercube Interconnection Networks
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- FPGAs Complete Fault Diagnosis Based on Binary Tree BIST Method
- Escape and Restoration Routing : Suspensive Deadlock Recovery in Interconnection Networks
- Low-Cost IP Core Test Using Tri-Template-Based Codes
- On the Activation Function and Fault Tolerance in Feedforward Neural Networks
- Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation(Dependable Computing)
- Proposal of Testable Multi-Context FPGA Architecture(Dependable Computing)
- Redundant Design for Wallace Multiplier(Dependable Computing)