A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory
スポンサーリンク
概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2000-04-30
著者
-
Hsu Charles
Microelectronics Laboratory Semiconductor Technology And Applicaiton Research (star) Group Departmen
-
Yang Evans
Microelectronics Laboratory Semiconductor Technology And Applicaiton Research (star) Group Departmen
-
Wong Wei-jer
Microelectronic Laboratory Semiconductor Technology Application Research(star)group Department Of El
-
Hsu Charles
Microelectronic Laboratory Semiconductor Technology Application Research(star)group Department Of El
-
King Y‐c
National Tsing-hua Univ. Hsin‐chu Twn
-
King Ya-chin
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
CHOU Amy
Microelectronic Laboratory, Semiconductor Technology Application Research(STAR)Group, Department of
-
WONG Wei-Zhe
Microelectronic Laboratory, Semiconductor Technology Application Research(STAR)Group, Department of
-
Wong Web-jer
Microelectronic Laboratory Semiconductor Technology Application Research(star)group Department Of El
-
Chou Amy
Microelectronic Laboratory Semiconductor Technology Application Research(star)group Department Of El
-
Yang Evans
Microelectronic Laboratory Semiconductor Technology Application Research(star)group Department Of El
-
King Ya-chin
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
YANG Evans
Microelectrics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University
-
HSU Charles
Microelectrics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University
関連論文
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- Low Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming
- CMOS-process-based ultra high density Flash Memory Cell and Array Architecture
- A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- A New Photodiode Structure with Optical Window for High-Sensitivity Complelnentary Metal Oxide Semiconductor (CMOS) Imagers
- A Body Effect Assisted NOR-Type (BeNOR) Multilevel Flash Memory
- Comprehensive Study of a New Self-Convergent Programming Scheme for Split Gate Flash Memory
- A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory
- Comprehensive Study of a New Self-Convergent Programming Scheme for Split Gate Flash Memory
- A New Bit-Line-Controlled Self-Convergent Multi-Level And-Type Flash Memory
- New Self-Convergent Programming Method for Multilevel AND Flash Memory
- New Self-Convergent Programming Method for Multi-Level AND Flash Memory
- Degradation of Flash Memory Using Drain-Avalanche Hot Electron (DAHE) Self-Convergence Operation Scheme
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices
- A New Ultra Low Voltage Silicon-Rich-Oxide (SRO) NAND Cell
- Self-Convergent Programming Scheme for Multilevel P-Channel Flash Memory
- Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor
- High Speed F-N Operated Volatile Memory Cell with Stacked Plasma Enhanced Chemical Vapor Deposition (PECVD) Nanocrystalline Si Layer Structure
- A Novel High-Density and High-Speed NAND-Type Electrical Erasable Programmable Read Only Memory
- A Novel High-Density and High-Speed NAND-Type EEPROM
- A Unified Functional Reliability Model for N-channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-μm CMOS Imagers
- Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric
- Optimization of Program Threshold Window from Understanding of Novel Fast Charge Loss in Nonvolatile Memory
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A Logarithmic Response Complementary Metal Oxide Semiconductor Image Sensor with Parasitic P–N–P Bipolar Junction Transistor
- Photodiode Model for CMOS Image Sensor SPICE Simulation
- Reliability and Memory Characteristics of Sequential Laterally Solidified Low Temperature Polycrystalline Silicon Thin Film Transistors with an Oxide–Nitride–Oxide Stack Gate Dielectric
- Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications
- Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process
- A New Photodiode Model for SPICE Simulation of Complementary Metal–Oxide–Semiconductor Image Sensors
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Sampling Scheme for High-Sensitivity, Extended-Dynamic-Range Complementary Metal Oxide Semiconductor (CMOS) Imaging Pixel Sensors
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process
- A Novel High-Density and High-Speed NAND-Type Electrical Erasable Programmable Read Only Memory
- Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices