High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications
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概要
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A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal–oxide–semiconductor (CMOS) logic process is presented. The cell which consists of two metal–oxide–semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to $10^{5}$ cycles, and 1000 h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.
- 2005-01-15
著者
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Lee Kung-hong
Microelectronics Laboratory Semiconductor Technology Application Research (star) Group Department Of
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King Ya-chin
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of
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King Ya-Chin
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University, Hsinchu 300, Taiwan, R.O.C.
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