King Ya-chin | Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
Low Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming
CMOS-process-based ultra high density Flash Memory Cell and Array Architecture
A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT
Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
A New Photodiode Structure with Optical Window for High-Sensitivity Complelnentary Metal Oxide Semiconductor (CMOS) Imagers
A Body Effect Assisted NOR-Type (BeNOR) Multilevel Flash Memory
Comprehensive Study of a New Self-Convergent Programming Scheme for Split Gate Flash Memory
A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory
A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor
New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-μm CMOS Imagers
Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric
A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
A Logarithmic Response Complementary Metal Oxide Semiconductor Image Sensor with Parasitic P–N–P Bipolar Junction Transistor
Photodiode Model for CMOS Image Sensor SPICE Simulation
Reliability and Memory Characteristics of Sequential Laterally Solidified Low Temperature Polycrystalline Silicon Thin Film Transistors with an Oxide–Nitride–Oxide Stack Gate Dielectric
Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications
Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process
A New Photodiode Model for SPICE Simulation of Complementary Metal–Oxide–Semiconductor Image Sensors
New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
A New Sampling Scheme for High-Sensitivity, Extended-Dynamic-Range Complementary Metal Oxide Semiconductor (CMOS) Imaging Pixel Sensors
A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process

もっと見る

スポンサーリンク