Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, a novel ballistic-injection AND-type (BiAND) split gate flash memory, with a trench select gate and buried n+ source is proposed. The ballistic source side injection (BSSI) programming mechanism is performed and realized in a contactless AND array, which features high programming efficiency, $10^{-3}$–$10^{-4}$ and small cell size of 5 F2. In addition, both the programming speed and read current is enhanced by the shared select gate structure. The BiAND flash memory is thus promising for low-voltage, high efficient, fast speed, scalable and high reliability non-volatile memory applications.
- 2006-02-15
著者
-
Wu Meng-yi
Microelectronics Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
King Ya-chin
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
HU Shu-Fen
National Nano Device Laboratory (NDL)
-
Wu Meng-Yi
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electronics Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan, R.O.C.
-
Yang Evans
eMemory Technology Inc., Hsin-Chu 300, Taiwan, R.O.C.
-
Dai Sheng-Huei
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electronics Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan, R.O.C.
-
Hsu Charles
eMemory Technology Inc., Hsin-Chu 300, Taiwan, R.O.C.
-
King Ya-Chin
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electronics Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan, R.O.C.
-
Hu Shu-Fen
National Nano Device Laboratory (NDL), Hsin-Chu 300, Taiwan, R.O.C.
関連論文
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- Low Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming
- CMOS-process-based ultra high density Flash Memory Cell and Array Architecture
- A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- A New Photodiode Structure with Optical Window for High-Sensitivity Complelnentary Metal Oxide Semiconductor (CMOS) Imagers
- A Body Effect Assisted NOR-Type (BeNOR) Multilevel Flash Memory
- Comprehensive Study of a New Self-Convergent Programming Scheme for Split Gate Flash Memory
- A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-μm CMOS Imagers
- Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A Logarithmic Response Complementary Metal Oxide Semiconductor Image Sensor with Parasitic P–N–P Bipolar Junction Transistor
- Photodiode Model for CMOS Image Sensor SPICE Simulation
- Reliability and Memory Characteristics of Sequential Laterally Solidified Low Temperature Polycrystalline Silicon Thin Film Transistors with an Oxide–Nitride–Oxide Stack Gate Dielectric
- Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications
- Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process
- A New Photodiode Model for SPICE Simulation of Complementary Metal–Oxide–Semiconductor Image Sensors
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Sampling Scheme for High-Sensitivity, Extended-Dynamic-Range Complementary Metal Oxide Semiconductor (CMOS) Imaging Pixel Sensors
- P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process
- Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor