P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance
スポンサーリンク
概要
- 論文の詳細を見る
Many high voltage complementary metal–oxide–semiconductor (HV-CMOS) processes are modified from a standard 5 V CMOS process by adding an N-type heavily doped layer under the P-well of a HV-PMOS drain terminal to isolate a high voltage P-well from a grounded P-substrate. The limitation of breakdown voltage is dominated by P-well concentration and junction depth. For designing a certain breakdown voltage ($\mathit{BV}_{\text{dss}}$) for a HV-PMOS, the original 5 V CMOS P-well concentration should be decreased, which could degrade 5 V CMOS characteristics, such as NMOS punch through and latch-up immunity. In this study, we demonstrate a novel HV-PMOS based on a split N-type buried layer (NBL), which provides a high $\mathit{BV}_{\text{dss}}$ in a HV-CMOS process. The newly proposed device with NBL split under the P-well of a drain electrode increases $\mathit{BV}_{\text{dss}}$ without degrading specific on-resistance ($R_{\text{on,sp}}$) and any added process complexity. From this result, P-well concentration could be increased to improve both 5 V NMOS characteristics and HV-PMOS $R_{\text{on,sp}}$.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-07-15
著者
-
King Ya-ching
Microelectronics Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
Lin Chrong
Microelectronics Lab., STAR Group, Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
-
Lin Ming-Jang
ANPEC Electronics Corporation, Hsinchu, Taiwan, R.O.C.
-
Lin Chrong
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C.
-
Hsu Charles
eMemory Technology Inc., Hsin-Chu 300, Taiwan, R.O.C.
-
Hsu Charles
eMemory Technology Inc., Hsinchu, Taiwan, R.O.C.
-
Liaw Chorng-Wei
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C.
-
Chang Ching-Hung
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C.
-
King Ya-Ching
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C.
関連論文
- A Unified Functional Reliability Model for N-channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub 2 nm Gate Oxide
- Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress
- Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
- Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process
- Trench Termination Design and Analysis in Low-Voltage N-Channel Trench Power Metal–Oxide–Semiconductor Field-Effect Transistor
- P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance
- A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process