Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, a transient voltage suppressor using a diode-activated SiGe heterojunction bipolar transistor (HBT) is proposed. The capacitance, DC current–voltage ($I$–$V$) characteristics, and transmission line pulse (TLP) $I$–$V$ characteristics of this combination device are investigated. An optimization guideline of the combination device is presented, verified by the corresponding simulation results, and a simple and effective method for achieving the target breakdown voltage is demonstrated. By combining the diode and SiGe HBT, the new structure exhibits both a low capacitance and a low breakdown voltage for protection against electrostatic discharge and electrical overstress in discrete or on-chip applications.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2009-04-25
著者
-
King Ya-chin
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Department Of
-
Lin Chrong-jung
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Institute Of E
-
Lin Chrong-Jung
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 30013, Taiwan
-
Dai Sheng-Huei
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electronics Engineering, National Tsing-Hua University, Hsin-Chu 300, Taiwan, R.O.C.
-
Dai Sheng-Huei
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 30013, Taiwan
-
Peng Jeng-Jie
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 30013, Taiwan
-
Chen Chia-Cheng
Microelectronics Laboratory, Semiconductor Technology Application Research (STAR) Group, Institute of Electronics Engineering, National Tsing-Hua University, Hsinchu 30013, Taiwan
関連論文
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- Low Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming
- CMOS-process-based ultra high density Flash Memory Cell and Array Architecture
- A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- A New Photodiode Structure with Optical Window for High-Sensitivity Complelnentary Metal Oxide Semiconductor (CMOS) Imagers
- A Body Effect Assisted NOR-Type (BeNOR) Multilevel Flash Memory
- Comprehensive Study of a New Self-Convergent Programming Scheme for Split Gate Flash Memory
- A New Bit-Line-Controlled Self-Convergent Multilevel AND-Type Flash Memory
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices
- A New Ultra Low Voltage Silicon-Rich-Oxide (SRO) NAND Cell
- Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor
- High Speed F-N Operated Volatile Memory Cell with Stacked Plasma Enhanced Chemical Vapor Deposition (PECVD) Nanocrystalline Si Layer Structure
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-μm CMOS Imagers
- Reliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- A Logarithmic Response Complementary Metal Oxide Semiconductor Image Sensor with Parasitic P–N–P Bipolar Junction Transistor
- Photodiode Model for CMOS Image Sensor SPICE Simulation
- Reliability and Memory Characteristics of Sequential Laterally Solidified Low Temperature Polycrystalline Silicon Thin Film Transistors with an Oxide–Nitride–Oxide Stack Gate Dielectric
- Comprehensively Study on a Ballistic-Injection AND-type Flash Memory Cell
- A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
- Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset
- Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture
- High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications
- Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process
- A New Photodiode Model for SPICE Simulation of Complementary Metal–Oxide–Semiconductor Image Sensors
- New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-Channel Metal-Oxide-Semiconductor Field Effect Transistors with Sub-3 nm Oxides
- A New Sampling Scheme for High-Sensitivity, Extended-Dynamic-Range Complementary Metal Oxide Semiconductor (CMOS) Imaging Pixel Sensors
- A Body-Effect-Assisted NOR-type (BeNOR) Multilevel Flash Memory
- Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal–Oxide–Semiconductor Process
- Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices
- Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor