Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices
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概要
- 論文の詳細を見る
In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1997-07-15
著者
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Lin Chrong-jung
Microelectronic Laboratory Semiconductor Technology Application Research (star) Group Institute Of E
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CHEN Hwi-Huang
United Microelectronics Cooperation
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Shen Shih-jye
Microelectronics Lab Semiconductor Technology And Application Research(star)group Department Of Elec
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HSU Charles
Microelectrics Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University
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Chen Hsin-Ming
Microelectronics Lab, Semiconductor Technology and Application Research (STAR) Group,
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Chen Hwi-Huang
United Microelectronics Cooperation, Hsin-Chu, Taiwan, ROC
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Hong Gary
United Microelectronics Cooperation, Hsin-Chu, Taiwan, ROC
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Lin Chrong-Jung
Microelectronics Lab, Semiconductor Technology and Application Research (STAR) Group,
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Shen Shih-Jye
Microelectronics Lab, Semiconductor Technology and Application Research (STAR) Group,
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