Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, <Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-μm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
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Kameyama Michitaka
Graduate School of Information Sciences, Tohoku University
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HARIYAMA Masanori
Graduate School of Information Sciences, Tohoku University
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Hariyama Masanori
Graduate School Of Information Sciences Tohoku University
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Hariyama Masanori
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Kameyama M
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science Tohoku University
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CHONG Weisheng
Graduate School of Information Sciences, Tohoku University
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CHONG Weisheng
Tohoku University
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Chong Weisheng
東北大学大学院情報科学研究科
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Hariyama M
Graduate School Of Information Sciences Tohoku University
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