Design and Evaluation of Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic

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概要

• 論文の詳細を見る

• A novel Multiple-Valued Field-Programmable VLSI (MV-FPVLSI) architecture is proposed and designed using Multiple-Valued Source-Coupled Logic (MVSCL) to implement special purpose processors. An MV-FPVLSI consists of identical cells, each of which is connected to 8-neighborhood ones through 1-bit switch block for each direction. An arbitrary 3-input logic operation is realized using the linear summation of the input currents and the threshold operations by the MVSCL circuits. A bit-serial pipeline architecture is introduced to reduce the interconnection complexity between the cells. As a result, the area of the switch-block between the cells becomes small. Further reduction of the switch-block area is possible by the linear summation of the input currents. Using 0.35μm CMOS standard design rule, a cell of the MV-FPVLSI is designed. Using HSPICE simulation tools, the cell is evaluated and compared with corresponding binary implementation. Comparison results show that, the delay of both cells are almost equal under normalized power consumption and the area of a cell, based on MVSCL, is 42% smaller than the binary one. That is, highly-parallel operations can be done using the MV-FPVLSI under total chip area constraint.

• 社団法人電子情報通信学会の論文
• 2004-12-10

著者

• Kameyama Michitaka

  Graduate School of Information Sciences, Tohoku University

• Haque Md.

  Graduate School Of Information Sciences Tohoku University

• Kameyama Michitaka

  Graduate School Of Information Science Tohoku University

• Kameyama Michitaka

  Graduate School Of Information Sciences Tohoku University

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