Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

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概要

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• The large data-transfer time among different cores is a big problem in heterogeneous multi-core processors. This paper presents a method to accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We used block matching, which is very common in image processing, to evaluate our technique. The proposed method reduces the data-transfer time by more than 42% compared to the earlier works that use CPU-based data transfers. Moreover, the total processing time is only 15ms for a VGA image with 16×16 pixel blocks.

著者

• Kameyama Michitaka

  Graduate School of Information Sciences, Tohoku University

• HARIYAMA Masanori

  Graduate School of Information Sciences, Tohoku University

• Hariyama Masanori

  Graduate School Of Information Sciences Tohoku University

• Waidyasooriya Hasitha

  Graduate School Of Information Sciences Tohoku University

• Uchiyama Kunio

  Central Research Laboratory Hitachi Ltd.

• Kameyama Michitaka

  Graduate School Of Information Science Tohoku University

• Hiramatsu Yoshitaka

  Central Research Laboratory Hitachi Ltd.

• WAIDYASOORIYA Hasitha

  Graduate School of Information Sciences, Tohoku University

• NOJIRI Toru

  Central Research Laboratory, Hitachi, Ltd.

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