Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions

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概要

• 論文の詳細を見る

• Accelerator cores in low-power embedded processors have on-chip multiple memory modules to increase the data access speed and to enable parallel data access. When large functional units such as multipliers and dividers are used for addressing, a large power and chip area are consumed. Therefore, recent low-power processors use small functional units such as adders and counters to reduce the power and area. Such small functional units make it difficult to implement complex addressing patterns without duplicating data among multiple memory modules. The data duplication wastes the memory capacity and increases the data transfer time significantly. This paper proposes a method to reduce the memory duplication for window-based image processing, which is widely used in many applications. Evaluations using an accelerator core show that the proposed method reduces the data amount and data transfer time by more than 50%.

• （社）電子情報通信学会の論文
• 2011-01-01

著者

• Hariyama Masanori

  Graduate School Of Information Sciences Tohoku University

• Hariyama Masanori

  The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku

• Waidyasooriya Hasitha

  Graduate School Of Information Sciences Tohoku University

• Kameyama M

  Graduate School Of Information Sciences Tohoku University

• Kameyama Michitaka

  Graduate School Of Information Science Tohoku University

• Hariyama M

  Graduate School Of Information Sciences Tohoku University

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