FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture(VLSI Architecture, <Special Section>VLSI Design and CAD Algorithms)

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概要

• 論文の詳細を見る

• This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor (Pentium4@2 GHz), and is enough to generate a 3-D depth image at the video rate of 33MHz.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• Kameyama Michitaka

  Graduate School of Information Sciences, Tohoku University

• Sasaki Haruka

  Graduate School Of Information Sciences Tohoku University

• HARIYAMA Masanori

  Graduate School of Information Sciences, Tohoku University

• KOBAYASHI Yasuhiro

  Oyama National College of Technology

• Hariyama Masanori

  Graduate School Of Information Sciences Tohoku University

• Kameyama Michitaka

  Tohoku Univ. Sendai‐shi Jpn

• Kameyama Michitaka

  Graduate School Of Information Science Tohoku University

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