A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates(<Special Section>Novel Device Architectures and System Integration Technologies)
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概要
- 論文の詳細を見る
Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause a large over-head in area when a number of contexts are used. To overcome the over-head, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35μcm CMOS-EPROM technology. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 13% in comparison with SRAM-based one. The total area of the proposed MC-FPGA is reduced to about 56% of that of a conventional SRAM-based MC-FPGA.
- 社団法人電子情報通信学会の論文
- 2006-11-01
著者
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Kameyama Michitaka
Graduate School of Information Sciences, Tohoku University
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Ogata Sho
Graduate Shcool Of Information Sciences Tohoku University
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HARIYAMA Masanori
Graduate School of Information Sciences, Tohoku University
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Hariyama Masanori
Graduate School Of Information Sciences Tohoku University
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Hariyama Masanori
Graduate Shcool Of Information Sciences Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science Tohoku University
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Kameyama Michitaka
Graduate Shcool Of Information Sciences Tohoku University
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