C-12-8 Design of a Very Compact Cell for a Multiple-Valued Fine-Grain Reconfigurable VLSI
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概要
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In this article we present the design of a very compact cell for a highly parallel multiple-valued fine-grain reconfigurable VLSI. The cell consists of a threshold logic gate, a dynamic latch and a switch block. A single Differential-Pair-Circuit (DPC) is used as a component of a comparator, where the comparator performs an arbitrary threshold logic operation. This leads to the high utilization of the cells because almost all the comparators in the VLSI chip can be utilized effectively without idle states. As a result, high parallelism can be achieved.
- 社団法人電子情報通信学会の論文
- 2006-03-08
著者
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Kameyama Michitaka
Graduate School of Information Sciences, Tohoku University
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Munirul Haque
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science Tohoku University
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