Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs (Special Issue on Super Chip for Intelligent Integrated Systems)
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概要
- 論文の詳細を見る
In digital control, it is essential to make the delay time for a large number of multiply-additions small because of sensor feedback. To meet the requirement, an architecture of the reconfigurable parallel processor using field-programmable gate arrays (FPGAs) is proposed. Although the performance is drastically increased in the full custum VLSI implementation, even the reconfigurable parallel processor using FPGAs becomes useful for many practical digital control applications. The performance evaluation shows that the delay time for the resolved acceleration control computation of a twelve-degrees-of-freedom (DOF) redundant manipulator becomes about 70 μs which is about seventeen times faster than that of a parallel processor approach using conventional digital signal processors (DSPs).
- 社団法人電子情報通信学会の論文
- 1994-07-25
著者
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Kameyama Michitaka
Graduate School of Information Sciences, Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science Tohoku University
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Fujioka Yoshichika
Graduate School of Information Sciences, Tohoku University
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Tomabechi Nobuhiro
Faculty of Engineering, Hachinohe Institute of Technology
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Tomabechi Nobuhiro
Faculty Of Engineering Hachinohe Institute Of Technology
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Fujioka Yoshichika
Graduate School Of Information Sciences Tohoku University
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