Design of Highly Parallel Linear Digital System for ULSI Processors (Special Issue on New Architecture LSIs)

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概要

• 論文の詳細を見る

• To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the alalytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

• 社団法人電子情報通信学会の論文
• 1993-07-25

著者

• Kameyama Michitaka

  Graduate School of Information Sciences, Tohoku University

• Nakajima Masami

  Graduate School Of Information Sciences Tohoku University

• Kameyama Michitaka

  Graduate School Of Information Science Tohoku University

• Kameyama Michitaka

  Graduate School Of Information Sciences:faculty Of Engineering Tohoku University

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