Kameyama Michitaka | Graduate School of Information Sciences, Tohoku University

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著作論文

Network coding-based reliable multicast scheme in wireless networks (無線通信システム)
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing
Design and Evaluation of Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture(VLSI Architecture, VLSI Design and CAD Algorithms)
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access(Digital Circuits and Computer Arithmetic, Recent Advances in Circuits and Systems-Part 1)
C-12-8 Design of a Very Compact Cell for a Multiple-Valued Fine-Grain Reconfigurable VLSI
Group Testing Based Detection of Web Service DDoS Attackers
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates(Novel Device Architectures and System Integration Technologies)
Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic(New System Paradigms for Integrated Electronics)
Design of Highly Parallel Linear Digital System for ULSI Processors (Special Issue on New Architecture LSIs)
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory (Special Issue on Multiple-Valued Logic)
Advanced VLSI Architecture for Intelligent Integrated Systems(Plenary Session,AWAD2006)
Advanced VLSI Architecture for Intelligent Integrated Systems(Plenary Session,AWAD2006)
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification(Novel Device Architectures and System Integration Technologies)
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, VLSI Design and CAD Algorithms)
C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages
Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture(New System Paradigms for Integrated Electronics)
Architecture of a high-performance stereo vision VLSI processor
A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition (Special Issue on Super Chip for Intelligent Integrated Systems)
Generalized Hough Transform VLSI Processor for Model-Based Edge Detection
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Memory Allocation for Multi-Resolution Image Processing
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs (Special Issue on Super Chip for Intelligent Integrated Systems)
Special Section on VLSI Technology toward Frontiers of New Market
A Minimum-Latency Linear Array FFT Processor for Robotics
Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size
Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel K-Ary Operation Circuits (Special Issue on New Architecture LSIs)
Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
Design of a CAM-Based Collision Detection VLSI Processor for Robotics (Special Issue on Super Chip for Intelligent Integrated Systems)
A Collision Detection Processor for Intelligent Vehicles (Special Issue on ASICs for Automotive Electronics)
Design Methodology for Human-Oriented Intelligent Integrated Systems
Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing (Special Issue on New Concept Device and Novel Architecture LSIs)
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

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