Kameyama Michitaka | Graduate School of Information Sciences, Tohoku University
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概要
関連著者
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Kameyama Michitaka
Graduate School of Information Sciences, Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science Tohoku University
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HARIYAMA Masanori
Graduate School of Information Sciences, Tohoku University
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Hariyama Masanori
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Tohoku Univ. Sendai‐shi Jpn
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Kameyama Michitaka
Graduate School Of Information Sciences Tohoku University
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Hariyama Masanori
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Kameyama M
Graduate School Of Information Sciences Tohoku University
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Hariyama M
Graduate School Of Information Sciences Tohoku University
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Hanyu Takahiro
Graduate School of Information Sciences, Tohoku University
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Hanyu Takahiro
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Graduate School Of Information Sciences And Also With The Faculty Of Engineering Tohoku University
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ISHIHARA Shota
Graduate School of Information Sciences, Tohoku University
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Ishihara Shota
Graduate School Of Information Sciences Tohoku University
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Jiang Xiaohong
Graduate School of Information Sciences, Tohoku University
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Sasaki Haruka
Graduate School Of Information Sciences Tohoku University
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Jiang Xiaohong
Graduate School Of Information Science Japan Advanced Institute Of Science And Technology Jaist
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Haque Md.
Graduate School Of Information Sciences Tohoku University
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KOBAYASHI Yasuhiro
Oyama National College of Technology
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Waidyasooriya Hasitha
Graduate School Of Information Sciences Tohoku University
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Tamaki Saneaki
Graduate School Of Engineering Tohoku University
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CHONG Weisheng
Graduate School of Information Sciences, Tohoku University
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CHONG Weisheng
Tohoku University
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Chong Weisheng
東北大学大学院情報科学研究科
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Zhang Zhiqiang
Graduate School of Information Sciences, Tohoku University
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Chi Kaikai
Graduate School of Information Sciences, Tohoku University
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Haque M
Graduate School Of Information Sciences Tohoku University
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Ogata Sho
Graduate Shcool Of Information Sciences Tohoku University
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Chi Kaikai
Graduate School Of Information Sciences Tohoku University
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Munirul Haque
Graduate School Of Information Sciences Tohoku University
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Fukushi Masaru
Graduate School Of Information Sciences Tohoku University
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Higuchi Tatsuo
Graduate School Of Information Sciences Tohoku University
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Jiang Xiaohong
Graduate School Of Information Science Tohoku University
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Jiang Xiaohong
Graduate School Of Information Sciences Tohoku University
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Watanabe Kan
Graduate School of Information Sciences, Tohoku University
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NASHAT Dalia
Graduate School of Information Science, Tohoku University
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Hariyama Masanori
Graduate Shcool Of Information Sciences Tohoku University
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Watanabe Kan
Graduate School Of Information Sciences Tohoku University
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Yokoyama Naoto
Graduate School Of Information Sciences Tohoku University
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Nakajima Masami
Graduate School Of Information Sciences Tohoku University
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SASAKI Yoshifumi
Faculty of Science and Technology, Ishinomaki Senshu University
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Nashat Dalia
Graduate School Of Information Science Tohoku University
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Yabe Y
Nec Corp. Sagamihara‐shi Jpn
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Hanyu Takahiro
Graduate School Of Information Sciences:faculty Of Engineering Tohoku University
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Tamaki S
Hitachi Ltd. Kodaira‐shi Jpn
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Zhang Zhiqiang
Graduate School Of Information Sciences Tohoku University
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Arakaki Manabu
Graduate School Of Information Sciences Tohoku University
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Higuchi Tatsuo
Graduate School Of Information Sciences And Faculty Of Engineering Tohoku University
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Uchiyama Kunio
Central Research Laboratory Hitachi Ltd.
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Kameyama Michitaka
Graduate Shcool Of Information Sciences Tohoku University
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YAMADERA Shigeo
Graduate School of Information Sciences, Tohoku University
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CHONG Wei
Graduate School of Information Sciences, Tohoku University
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LEE Seunghwan
Graduate School of Information Sciences, Tohoku University
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Sasaki Yoshifumi
Graduate School of Information Sciences, Tohoku University
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Yusuf Muhammad
Graduate School of Information Sciences,Tohoku University
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OKADA Nobuaki
Graduate School of Information Science, Tohoku University
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Fujioka Yoshichika
Graduate School of Information Sciences, Tohoku University
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Tomabechi Nobuhiro
Faculty of Engineering, Hachinohe Institute of Technology
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Kameyama Michitaka
Graduate School Of Information Sciences:faculty Of Engineering Tohoku University
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Kameyama Michitaka
Graduate School Of Information Science:faculty Of Engineering Tohoku University
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Kameyama Michitaka
Graduate School Of Information Sciences And Faculty Of Engineering Tohoku University
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Lee Seunghwan
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Kittichaikoonkit Somchai
Graduate School of Engineering, Tohoku University
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Yabe Yoshikazu
Graduate School of Information Sciences, Tohoku University
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Chong Wei
Graduate School Of Information Sciences Tohoku University
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Okada Nobuaki
Graduate School Of Information Science Tohoku University
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Yusuf Muhammad
Graduate School Of Information Sciences Tohoku University
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Yamadera Shigeo
Graduate School Of Information Sciences Tohoku University
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Tamaki S
Graduate School Of Engineering Tohoku University
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Michitaka Kameyama
Graduate School Of Information Sciences Tohoku University
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KOMATSU Yoshiya
Graduate School of Information Sciences, Tohoku University
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IDOBATA Noriaki
Graduate School of Information Sciences, Tohoku University
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Sasaki Yoshifumi
Faculty Of Science And Technology Ishinomaki Senshu University
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Tomabechi Nobuhiro
Faculty Of Engineering Hachinohe Institute Of Technology
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Fujioka Yoshichika
Graduate School Of Information Sciences Tohoku University
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Kittichaikoonkit Somchai
Graduate School Of Engineering Tohoku University
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Idobata Noriaki
Graduate School Of Information Sciences Tohoku University
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Komatsu Yoshiya
Graduate School Of Information Sciences Tohoku University
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Hiramatsu Yoshitaka
Central Research Laboratory Hitachi Ltd.
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Kameyama Michitaka
Graduate School of Information Sciences,Tohoku University
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Dalia NASHAT
Graduate School of Information Science, Tohoku University
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WAIDYASOORIYA Hasitha
Graduate School of Information Sciences, Tohoku University
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Kameyama Michitaka
Graduate School of Information Sciences, and also with the Faculty of Engineering, Tohoku University
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NOJIRI Toru
Central Research Laboratory, Hitachi, Ltd.
著作論文
- Network coding-based reliable multicast scheme in wireless networks (無線通信システム)
- Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing
- Design and Evaluation of Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic
- FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture(VLSI Architecture, VLSI Design and CAD Algorithms)
- Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access(Digital Circuits and Computer Arithmetic, Recent Advances in Circuits and Systems-Part 1)
- C-12-8 Design of a Very Compact Cell for a Multiple-Valued Fine-Grain Reconfigurable VLSI
- Group Testing Based Detection of Web Service DDoS Attackers
- A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates(Novel Device Architectures and System Integration Technologies)
- Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic(New System Paradigms for Integrated Electronics)
- Design of Highly Parallel Linear Digital System for ULSI Processors (Special Issue on New Architecture LSIs)
- Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinational Circuits Based on Partition Theory (Special Issue on Multiple-Valued Logic)
- Advanced VLSI Architecture for Intelligent Integrated Systems(Plenary Session,AWAD2006)
- Advanced VLSI Architecture for Intelligent Integrated Systems(Plenary Session,AWAD2006)
- Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
- Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification(Novel Device Architectures and System Integration Technologies)
- Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, VLSI Design and CAD Algorithms)
- C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages
- Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture(New System Paradigms for Integrated Electronics)
- Architecture of a high-performance stereo vision VLSI processor
- A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition (Special Issue on Super Chip for Intelligent Integrated Systems)
- Generalized Hough Transform VLSI Processor for Model-Based Edge Detection
- Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
- Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
- Memory Allocation for Multi-Resolution Image Processing
- Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
- Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs (Special Issue on Super Chip for Intelligent Integrated Systems)
- Special Section on VLSI Technology toward Frontiers of New Market
- A Minimum-Latency Linear Array FFT Processor for Robotics
- Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size
- Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel K-Ary Operation Circuits (Special Issue on New Architecture LSIs)
- Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
- Design of a CAM-Based Collision Detection VLSI Processor for Robotics (Special Issue on Super Chip for Intelligent Integrated Systems)
- A Collision Detection Processor for Intelligent Vehicles (Special Issue on ASICs for Automotive Electronics)
- Design Methodology for Human-Oriented Intelligent Integrated Systems
- Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing (Special Issue on New Concept Device and Novel Architecture LSIs)
- An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
- A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
- Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation