Kameyama Michitaka | Tohoku Univ. Sendai‐shi Jpn

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著作論文

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture(VLSI Architecture, VLSI Design and CAD Algorithms)
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access(Digital Circuits and Computer Arithmetic, Recent Advances in Circuits and Systems-Part 1)
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
Memory Allocation for Multi-Resolution Image Processing
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture

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