Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

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概要

• 論文の詳細を見る

• Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.

• （社）電子情報通信学会の論文
• 2008-04-01

著者

• Hariyama Masanori

  The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku

• Waidyasooriya Hasitha

  Graduate School Of Information Sciences Tohoku University

• Kameyama M

  Graduate School Of Information Sciences Tohoku University

• Kameyama Michitaka

  Tohoku Univ. Sendai‐shi Jpn

• WAIDYASOORIYA Hasitha

  Tohoku University

• HARIYAMA Masanori

  Tohoku University

• CHONG Weisheng

  Tohoku University

• Chong Weisheng

  東北大学大学院情報科学研究科

• Hariyama M

  Graduate School Of Information Sciences Tohoku University

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