複数電源電圧を用いた低消費電カフィールドプログラマブルVLSI(ディジタル・情報家電,放送用,ゲーム機器用システムLSI及び一般)

概要

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This paper proposes a low-power field-programmable VLSI processor (FPVLSI) to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). Large power consumption in FPGAs is mainly caused by complex routing networks. To reduce the complexity of routing networks, an area-efficient bit-serial pipeline architecture is introduced in the FPVLSI. A fine-grain supply-voltage-control scheme is proposed where a supply voltage of each logic block is programmable. To realize the scheme in an area-efficient way, a level-converter-less logic block using dynamic circuits is presented. The FPVLSI is evaluated based on a 0.18-^m CMOS design rule. The power consumption of the FPVLSI is reduced to 40% compared to that of the FPGA.
社団法人電子情報通信学会の論文
2004-09-03