An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
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概要
- 論文の詳細を見る
In designing a field-programmable gate array(FPGA)-based processor for motion stereo, a parallel memory system and a simple interconnection network for parallel data transfer are essential for parallel image processing. This paper, firstly, presents an FPGA-oriented hierarchical memory system. To reduce the bandwidth requirement between an on-chip memory in an FPGA and external memories, we propose an efficient scheduling:Once pixels are transferred to the on-chip memory, operations associated with the data are consecutively performed. Secondly, a rectangular memory allocation is proposed which allocates pixels to be accessed in parallel onto different memory modules of the on-chip memory. Consequently, completely parallel access can be achieved. The memory allocation also minimizes the required capacity of the on-chip memory and thus is suitable for FPGA-based implementation. Finally, a functional unit allocation is proposed to minimize the complexity between memory modules and functional units. An experimental result shows that the performance of the processor becomes 96 times higher than that of a 400MHz Pentium II.
- 社団法人電子情報通信学会の論文
- 2000-12-25
著者
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Hariyama Masanori
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Kameyama M
Graduate School Of Information Sciences Tohoku University
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LEE Seunghwan
the Department of computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
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KAMEYAMA Michitaka
the Department of computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
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Lee Seunghwan
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Hariyama M
Graduate School Of Information Sciences Tohoku University
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