Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
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概要
- 論文の詳細を見る
This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.
- （社）電子情報通信学会の論文
- 2008-12-01
著者
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Hariyama Masanori
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
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Waidyasooriya Hasitha
Graduate School Of Information Sciences Tohoku University
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Kameyama M
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Tohoku Univ. Sendai‐shi Jpn
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WAIDYASOORIYA Hasitha
Tohoku University
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HARIYAMA Masanori
Tohoku University
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Hariyama M
Graduate School Of Information Sciences Tohoku University
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