Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
スポンサーリンク
概要
- 論文の詳細を見る
In a real-time vision system, parallel memory access is essential for highly parallel image processing. The use of multiple memory modules is one efficient technique for parallel access. In the technique, data stored in different memory modules can be accessed in parallel. This paper presents an optimal memory allocation methodology to map data to be read in parallel onto different memory modules. Based on the methodology, a high-performance VLSI processor for three-dimensional instrumentation is proposed.
- 社団法人電子情報通信学会の論文
- 2001-03-01
著者
-
Hariyama Masanori
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
-
Kameyama M
Graduate School Of Information Sciences Tohoku University
-
LEE Seunghwan
the Department of computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
-
KAMEYAMA Michitaka
the Department of computer and Mathematical Sciences, Graduate School of Information Sciences, Tohok
-
Lee Seunghwan
The Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku
-
Hariyama M
Graduate School Of Information Sciences Tohoku University
関連論文
- Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
- Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System(Special Issue on High-Performance and Low-Power Microprocessors)
- Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, VLSI Design and CAD Algorithms)
- Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture(New System Paradigms for Integrated Electronics)
- Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
- An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
- Architecture of a high-performance stereo vision VLSI processor
- Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory
- A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
- Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
- Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
- Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
- Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
- Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors : A Case Study of HOG Descriptor Computation
- Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors