Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
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概要
- 論文の詳細を見る
This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-μm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.
- 社団法人電子情報通信学会の論文
- 2002-10-01
著者
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Kimura Hiromitsu
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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HANYU Takahiro
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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KAMEYAMA Michitaka
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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Kimura H
Ntt Access Network Service Systems Laboratories
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Hanyu T
Tohoku Univ. Sendai‐shi Jpn
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Kameyama M
Graduate School Of Information Sciences Tohoku University
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Kameyama Michitaka
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Hanyu Takahiro
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Kimura Hiromitsu
Department Of Chemistry Graduate School Of Science Tohoku University
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