Design and Architecture for Low-Power/High-Speed RISC Microprocessor : SuperH (Special Issue on Low-Power and High-Speed LSI Technologies)
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概要
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This paper describes the design and architecture for a newly developed microprocessor suitable for consumer applications, which we call SuperH. To achieve both low-power and high-speed, the SuperH architecture includes 16-bit fixed length instruction code and several power saving features. The 16-bit fixed length instruction code makes the SuperH possible to achieve excellent code efficiency for the SPECint benchmarks when compared with conventional microcontrollers and RISC's for workstations and PC's. As a result, the SuperH provides almost the same code efficiency as that of 8-bit microcontrollers, and also achieves similar performance as that of RISC's with 32-bit fixed length instruction code. The SuperH also incorporates several power reduction techniques through the control of clock frequency and clock distribution. Thus, the 16-bit code format, power saving features, and other architectural innovations make the SuperH particularly proficient for portable multi-media applications.
- 社団法人電子情報通信学会の論文
- 1997-12-25
著者
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Kainaga Masahiro
Semiconductor Technology Development Center Semiconductor & Ic Division Hitachi Ltd.
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MAEJIMA Hideo
Semiconductor Technology Development Center Semiconductor & IC Division, Hitachi, Ltd.
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UCHIYAMA Kunio
Central Research Laboratory, Hitachi, Ltd.
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Maejima H
Semiconductor Technology Development Center Semiconductor & Ic Division Hitachi Ltd.
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Maejima Hideo
Semiconductor & Integrated Circuits Division
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Uchiyama Kunio
Central Research Laboratory Hitachi Ltd.
関連論文
- Design and Architecture for Low-Power/High-Speed RISC Microprocessor : SuperH (Special Issue on Low-Power and High-Speed LSI Technologies)
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- Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products(Special Issue on High-Performance and Low-Power Microprocessors)
- An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors (Special Issue on low-Power LSI Technologies)
- Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
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