An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors (Special Issue on low-Power LSI Technologies)

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概要

• 論文の詳細を見る

• An embedded cache memory for low power RISC microprocessors is described. An automatic-power-save architecture (APSA) enables the cache memory to operate with high speed at high frequencies, and with low power dissipation at low frequencies. A pulsed word technique (PWT) and an isolated bit line technique (IBLT) reduce the power dissipation of the cache memory effectively. Using these three techniques,the power dissipation of the cache memory is reduced to almost 60% of the conventional cache memory at 60 MHz and to 20% at a clock frequency of l0 MHz. An 8 KByte test chip using 0.5μm CMOS technology was fabricated, and it achieves 80 MHz operation at a supply voltage of 3.1 V, and 8 mW operation at a supply voltage of 2.5 V at l0 MHz.

• 社団法人電子情報通信学会の論文
• 1996-12-25

著者

• ISHIBASHI Koichiro

  Central Research Laboratory, Hitachi, Ltd.

• Maejima Hideo

  Semiconductor & Integrated Circuits Division

• Shimazaki Yasuhisa

  Semiconductor & Integrated Circuits Division Hitachi Ltd.

• NORISUE Katsuhiro

  Semiconductor & Integrated Circuits Division, Hitachi Ltd.

• Norisue Katsuhiro

  Semiconductor & Integrated Circuits Division Hitachi Ltd.

• Ishibashi Koichiro

  Central Research Laboratory Hitachi Ltd.

• ISHIBASHI Koichiro

  Central Research Laboratory,Hitachi Ltd.

関連論文

• A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
• A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
• Design and Architecture for Low-Power/High-Speed RISC Microprocessor : SuperH (Special Issue on Low-Power and High-Speed LSI Technologies)
• Quantitative Study of an SA-Vt CMOS Circuit : Evaluation of Fluctuation in Device and Circuit Performance
• Analog Circuit Design Methodology in a Low Power RISC Microprocessor (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)
• A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
• A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
• An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors (Special Issue on low-Power LSI Technologies)
• High-Speed CMOS SRAM Technologies for Cache Applications (Special Issue on ULSI Memory Technology)
• CMOS Process Compatible ie-Flash(Inverse Gate Electrode Flash)Technology for System-on-a Chip(Special Issue on Nonvolatile Memories)

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