A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
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概要
- 論文の詳細を見る
We fabricated a 16-kB cache macro using 0.35-μm quadruple-metal CMOS technology.This is a 285-MHz, two-port 16-kB(512×256b)cache macro that has a 2-ns access time.This high-speed performance is enabled by a hierarchical bit-line architecture that uses double global bit-line pairs(WGBs), and a high-speed timing-insensitive sense amplifier(ISA)that shortens the access time.
- 社団法人電子情報通信学会の論文
- 2000-01-25
著者
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Osada K
Japan Broadcasting Corp. Tokyo Jpn
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HASHIMOTO Naotaka
Semiconductor & Integrated Circuits Division, Hitachi Ltd.
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ISHIBASHI Koichiro
Central Research Laboratory, Hitachi, Ltd.
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Higuchi H
Hitachi Ltd. Hadano‐shi Jpn
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HIGUCHI Hisayuki
Central Research Laboratory, Hitachi Ltd.
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SHIOZAWA Kenji
Semiconductor and IC Division, Hitachi Ltd.
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OSADA Kenichi
Central Research Laboratory, Hitachi, Ltd.
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Shiozawa K
Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Higuchi Hisayuki
Central Research Laboratory Hitachi Ltd.
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Ishibashi K
Riken Wako‐shi Jpn
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Ishibashi Koichiro
Central Research Laboratory Hitachi Ltd.
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SHIOZAWA Kenji
Semiconductor & Integrated Circuits Division, Hitachi Ltd.
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