Ishibashi Koichiro | Central Research Laboratory Hitachi Ltd.

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著作論文

A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
Quantitative Study of an SA-Vt CMOS Circuit : Evaluation of Fluctuation in Device and Circuit Performance
Analog Circuit Design Methodology in a Low Power RISC Microprocessor (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)
A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors (Special Issue on low-Power LSI Technologies)
High-Speed CMOS SRAM Technologies for Cache Applications (Special Issue on ULSI Memory Technology)
CMOS Process Compatible ie-Flash(Inverse Gate Electrode Flash)Technology for System-on-a Chip(Special Issue on Nonvolatile Memories)

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