Higuchi Hisayuki | Central Research Laboratory Hitachi Ltd.
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概要
関連著者
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Higuchi Hisayuki
Central Research Laboratory Hitachi Ltd.
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MIZUO Shoichi
Central Research Laboratory, Hitachi Ltd.
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Mizuo Shoichi
Central Research Laboratory Hitachi Ltd.
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HIGUCHI Hisayuki
Central Research Laboratory, Hitachi Ltd.
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HASHIMOTO Naotaka
Semiconductor & Integrated Circuits Division, Hitachi Ltd.
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ISHIBASHI Koichiro
Central Research Laboratory, Hitachi, Ltd.
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Higuchi H
Hitachi Ltd. Hadano‐shi Jpn
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SHIOZAWA Kenji
Semiconductor and IC Division, Hitachi Ltd.
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Shiozawa K
Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Ishibashi K
Riken Wako‐shi Jpn
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Ishibashi Koichiro
Central Research Laboratory Hitachi Ltd.
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SHIOZAWA Kenji
Semiconductor & Integrated Circuits Division, Hitachi Ltd.
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Osada K
Japan Broadcasting Corp. Tokyo Jpn
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Mizuno Shoichi
Central Research Laboratory Hitachi Ltd.
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IKEDA Shuji
Semiconductor & Integrated Circuits Division, Hitachi Ltd.
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NAGANO Takahiro
Semiconductor and Integrated Circuits Division, Hitachi, Ltd.
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Ikeda Shuji
Semiconductor And Integrated Circuit Division Hitachi Ltd.
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Ikeda Shuji
Semiconductor & Integrated Circuits Div. Hitachi Ltd.
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Minami M
Keio Univ. Fujisawa‐shi Jpn
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Nagano T
Hitachi Ulsi Systems Co. Ltd. Kodaira‐shi Jpn
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Nitta Takahisa
Device Development Center Hitachi Ltd.
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UCHIYAMA Kunio
Central Research Laboratory, Hitachi, Ltd.
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Uchiyama K
Hitachi Ltd. Kokubunji‐shi Jpn
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Uchiyama Kunio
Central Research Laboratory Hitachi Ltd.
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SHIMBO Toshinobu
Hitachi ULSI Engineering Corporation
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OSADA Kenichi
Central Research Laboratory, Hitachi, Ltd.
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Minami Masataka
Semiconductor And Integrated Circuits Division Hitachi Ltd.
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MAKI Michiyoshi
Central Research Laboratory, Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory, Hitachi Ltd.
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AKAHANE Ryouzou
Naka Works, Hitachi Ltd.
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Akahane Ryouzou
Naka Works Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory Hitachi Ltd.
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Maki Michiyoshi
Central Research Laboratory Hitachi Ltd.
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Nagano Takahiro
Semiconductor And Integrated Circuits Division Hitachi Ltd.
著作論文
- Analog Circuit Design Methodology in a Low Power RISC Microprocessor (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)
- Preservation of Point Defect Distribution in FZ Silicon
- A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
- A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits (Special Issue on ULSI Memory Technology)
- Quanititative Study of Implanted Gold Atoms in Silicon p^+-n Junctions by Measurement of the Thermally-Stimulated Current
- Observations of Channels of MOS Field Effect Transistors Using a Scanning-Electron Microscope
- The Range of Diffusion Enhancement of B and P in Si during Thermal Oxidation
- Effects of Backside Oxidation on the Size of Oxidation Induced Stacking Faults at the Front Surface of FZ Si Wafers
- Suppression by Pre-Diffusion Annealing of Anomalous Diffusion of B and P in Si Directly Masked with Si_3N_4 Films
- Effects of Oxidation on Aluminum Diffusion in Silicon
- Retardation of Sb Diffusion in Si during Thermal Oxidation
- Anomalous Diffusion of B and P in Si Directly Masked with Si_3N_4
- Anomalous Phosphorus Diffusion in Si Directly Masked with Si_3N_4 Films