HASHIMOTO Naotaka | Semiconductor & Integrated Circuits Division, Hitachi Ltd.

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A High Performance p-Channel Transistor:β-MOS FET
A High Performance p-Channel Transistor : β-MOS FET
A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
Analog Circuit Design Methodology in a Low Power RISC Microprocessor (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)
A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
A High Performance p-Channel Transistor: β-MOS FET

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