YAMANAKA Toshiaki | Central Research Laboratory, Hitachi, Ltd.

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著作論文

Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit
A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells
Large 1/f Noise in Polysilicon TFT Loads and Its Effects on the Stability of SRAM Cells
A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers(Special Issue on the 1994 VLSI Circuits Symposium)
A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits(Special Issue on the 1994 VLSI Circuits Symposium)

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