A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits(Special Issue on the 1994 VLSI Circuits Symposium)
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概要
- 論文の詳細を見る
The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM, and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6ns.
- 社団法人電子情報通信学会の論文
- 1995-06-25
著者
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YAMANAKA Toshiaki
Central Research Laboratory, Hitachi, Ltd.
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Takasugi Koichi
Semiconductor and Integrated Circuit Division, Hitachi Ltd.
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Nakagome Yoshinobu
Central Research Laboratory Hitachi Ltd.
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Nakagome Yoshinobu
Central Research Laboratory
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Sasaki Katsuro
Central Research Laboratory Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory, Hitachi Ltd.
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Higuchi Hisayuki
ULSI Research Center, Hitachi Ltd.
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Takasugi Koichi
Semiconductor And Integrated Circuit Division Hitachi Ltd.
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Higuchi Hisayuki
Ulsi Research Center Hitachi Ltd.
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Yamanaka Toshiaki
Central Research Laboratory Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory Hitachi Ltd.
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