A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits (Special Issue on ULSI Memory Technology)
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概要
- 論文の詳細を見る
Low-power, high-speed match-detection circuits for a content addressable memory (CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns match-detection time with 5-mW power dissipation in 10-ns cycle-time.
- 社団法人電子情報通信学会の論文
- 1996-06-25
著者
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NAGANO Takahiro
Semiconductor and Integrated Circuits Division, Hitachi, Ltd.
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Minami M
Keio Univ. Fujisawa‐shi Jpn
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Nagano T
Hitachi Ulsi Systems Co. Ltd. Kodaira‐shi Jpn
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Minami Masataka
Semiconductor And Integrated Circuits Division Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory, Hitachi Ltd.
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Higuchi Hisayuki
Central Research Laboratory Hitachi Ltd.
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Tachibana Suguru
Central Research Laboratory Hitachi Ltd.
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Nagano Takahiro
Semiconductor And Integrated Circuits Division Hitachi Ltd.
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