Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit
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概要
- 論文の詳細を見る
We have observed a unique phenomenon during low-gate voltage (V G) static stressing of metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Static stressing has been performed by probing n-MOSFET devices that are discrete, as well as devices that are embedded in a circuit. Although the measured substrate current for the circuit and discrete devices is similar, significantly more hole trapping is observed under low-V G static stressing of circuit devices. It is clear that the extent of hole trapping is circuit dependent, and that in actual operation the devices will not undergo such static stressing. Nevertheless, these devices provided a unique opportunity to study the role of hole trapping in interface-state formation. Thus, rather than identifying the cause for increased hole trapping, we focused our efforts on understanding the mechanisms of interface-state formation. It is found that while both electrons and holes are needed for the formation of interface states, it is hole trapping that is the rate-limiting factor in device degradation.
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 1997-07-15
著者
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Gupta Ashawant
Microelectronics Laboratory Santa Clara University
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Sugiharto Dewi
Microelectronics Laboratory Santa Clara University
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Matsuzaki Nozomu
Central Research Laboratory Hitachi Ltd.
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Yang Cary
Microelectronics Lab. Santa Clara University
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Minami Masataka
Central Research Laboratory Hitachi Ltd.
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Yamanaka Toshiaki
Central Research Laboratory Hitachi Ltd.
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Nagano Takahiro
Central Research Laboratory Hitachi Ltd.
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Yang Cary
Microelectronics Laboratory, Santa Clara University, Santa Clara, CA 95053, USA
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Gupta Ashawant
Microelectronics Laboratory, Santa Clara University, Santa Clara, CA 95053, USA
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Minami Masataka
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan
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Matsuzaki Nozomu
Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan
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Sugiharto Dewi
Microelectronics Laboratory, Santa Clara University, Santa Clara, CA 95053, USA
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- Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit
- Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells