Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

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概要

• 論文の詳細を見る
• 2012-12-01

著者

• Uchiyama Kunio

  Central Research Laboratory Hitachi Ltd.

• HARIYAMA Masanori

  the Graduate School of Information Sciences, Tohoku University

• Kameyama Michitaka

  The Graduate School Of Information Sciences And Also With The Faculty Of Engineering Tohoku Universi

• Hiramatsu Yoshitaka

  Central Research Laboratory Hitachi Ltd.

• NOJIRI Toru

  Central Research Laboratory, Hitachi, Ltd.

• WAIDYASOORIYA Hasitha

  the Graduate School of Information Sciences, Tohoku University

関連論文

• Design and Architecture for Low-Power/High-Speed RISC Microprocessor : SuperH (Special Issue on Low-Power and High-Speed LSI Technologies)
• Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
• A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
• Unified Scheduling of High Performance Parallel VLSI Processors for Robotics (Special Section on JTC-CSCC '92)
• Analog Circuit Design Methodology in a Low Power RISC Microprocessor (Srecial Section on Analong Circuit Tectningues in the Digital-oriented Era)
• Detection of Fundus Lesions Using Classifier Selection
• Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products(Special Issue on High-Performance and Low-Power Microprocessors)
• Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
• Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates
• Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation

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